06 Adders

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Transcript

Chapter Six adders. As we progress along in the study of combinational logic, we now have arrived at the point where we would like to do some arithmetic combinational logic. Remember how addition works in the binary system, a zero plus a zero will equal a zero, a one plus a zero will equal a one, and a zero plus a one will equal a one. A one plus a one will equal a zero, but it's intimated that there is a carry one to the next most significant digit. If we are looking at a single bit register, the digit one in the sum could not exist. Because there's no room for it, there's only a single bit there.

But we would like to remember it in some way. We can do this with an extra term, which we'll call C, for carry. And let's assign a variable to the two items that we're adding together the A and the B. So it's a plus b. And we will assume the output is for the register is sigma, we will call it sigma for variable sign. And we can assign a truth table to this.

So that if we do the very, very A and B 00011011, we have a unique output for each one of the variables a and b, so a 00 sigma would be zero. The carry would be A zero. If a was zero and B was one, the sum would be one and there'd still be no carry. Again, if A is one and B is zero, then the sum is one and there's still no carry. However, in the event that we have a is equal to one, b is equal to one, then sigma would have to be zero, but we want to carry one. So this truth table describes what we are looking for in the way of a matter.

This binary arithmetic is carried out by the combinational gate logic the simplest of which is shown here. This circuit consists in its most basic form of two gates, and exclusive OR gate that produces a logic one output whenever a and b are different and The endgame producer logic one at the carry output when both A and B are one. We call this a half adder. And I'll explain that in a moment. The logic of the truth table still holds true, zero, a and zero at a and zero at B, when added together will give a zero. A zero at a and a one at B will give a one output a one at a and a zero at B will give a one output and a one at a and a one at B will give a zero but it'll give a one output on the C output.

So the truth table holds true. As with flip flops, the combinational gate logic can be replaced by the hash adder function. And they exist in package form. And they look like this. They have two inputs A and a B, and two outputs a sigma or some output and a carry output. Now, the half adder as it names in name its name implies is not complete, it is fine for adding to one bit numbers together, but for a binary number containing several bits I carry in must be allowed as well as a carry out as half adders have only two inputs it cannot add a carry in to the composition.

So, it is not practical for carrying out anything but adding a single bit. What we need is what is called a full adder when two or more bits are to be added the circuit used is a full adder, which is shown here. This circuit simply comprises two half adders. The Sum of a and b from the first half adder is used as a sigma one input to the second half adder, which now produces a sum of the first half adder plus any carry in from the C in Terminal. Any carries produced by the two half adders are then read together to produce a single c out output. As before, the combinational gate logic can be represented by a full adder function which looks like this.

It has three inputs and two outputs the inputs being a and b plus any carries that are coming from a previous register. Karis in. So there's three inputs A, B and C n, and two outputs which is the sum plus any carries that have to be kept carried over to the next register. The truth table for this function is shown here. And you can see without going through each one individually, that this indeed gives us the full edition with any of the possibilities of a carry in and a carry out. full adders can now be stacked, in this case to carry out a function of what we call parallel adders.

In order to do binary addition. The two inputs are made up of a series of four bit inputs and four bit B inputs when added together, Give us a sum, which is given by S naught through s three. Parallel adders can be built in several forms to add multi bit binary numbers each bit of the parallel adder using a single full adder circuit, as parallel adder circuits would look quite complex if drawing drawn using individual gates. It's quite common as in this case, to use or replace the full adder gates with a schematic diagram or a block indicating a full adder. This slide will illustrate how a number of full adders can be combined to make a parallel adder also called a ripple carry adder because of the way that any carry ripples through to the next bit. Let's look at the first bit which is the A naught bit of The adder, so you get an A knot input and a B naught input, which goes through the adder, the full adder to give a sum s zero on the output.

The next bit, takes a one and adds it to be one, but it also takes the carry out from the previous bit and is the C in for the second bit. So it's adding a and b plus the carry in to give us an s one output. And it'll also provide a carry out if indeed there is one present. So the next bit will do the same thing. It'll Connect, in this case, a B two and an A to plus the carry in from the carry out of the previous bit. And the same thing happens with the most significant Bit, adding the a three and the v3 together, taking the carry out from the previous bed and adding it on a carry in basis to give us the number we're looking for.

Just as a point of information here, in the case of the least significant bit, we could have used a half adder in this location as to be as opposed to be using a full adder because we don't have any registers previous to this one that might be bringing a carry into it. So the carry in function is superfluous in this case, so this possibly could be replaced by a half adder. But quite frankly, the costs of the cost difference between using half In full adders is probably pretty small. And especially if you want to start adding a one half adder to a circuit, it might even be more expensive to do so. So in this case, the carry in position would probably be grounded to a, have a zero input on the carry in spot and just use a full adder in but only taking the A and a B in to consideration and the CN would then be zero at all times.

This ends chapter six

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