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Clock Delay Operator

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Transcript

Hello and welcome to lecture number nine. Starting this lecture, we will see all the concurrent assertion operators, ADA, these are the operators that pretty much make up the bulk of the language and there are quite a few of those. We will look at those mostly in single lectures or maybe a few of them combined in a single lecture. So let's start with the clock delay operator that we have actually seen a few times. But for the sake of completeness, here's the lb lb m delay operator m can be zero here that means there is no delay, or m can be a positive integer. Obviously, time cannot advance backwards so you cannot be negative integers.

And as I've said before in previous lectures, do not confuse this with the Verilog pound delay. Luckily, the syntax is that there are two pounds signs here. So the chances of mistake are very less. So in this property, we have seen this property many times before. Here's a property at pauses of clock z implies if G's true implies starting the same clock, this sequence should hold. And that sequence basically say a must be followed by B, two clocks later, we assert the property, and then we cover the property.

And if during a search, and if it fails, we call this task and didn't cover if it is covered the meaning if it passes, then we call this task. So here's a very simple log of this property that I've simulated. And as you can see at Paul's edge of clock apes, is one that a must be one at the same clock and B should be one two clocks later that indeed happens here and the property policies here, clock is one at pauses of clock Z's one and A's also on exactly as required, but these not want to translator in the property fails. Further duress for the rest of the lectures in this course, I will not be showing this particular code because I'm going to use this code pretty much everywhere. In short, I will only show the sequence and property and then I will show you a log with pass and fail.

Whether this pass and fail come from it comes from this code. So I assume that this code exists and during the rest of the lecture Okay, now let's look at the clock delay range operator. So, here we are saying that in this sequence A, B must follow a reading 123 clocks, it can follow a one talk later or two clocks later, one clock later or two clocks later or three clocks later. That's why it's called a range delay operator and can be zero and can be zero or in finite. And I will show you an example on how we find that actually works. And obviously if it is 00 colon zero is the same as zero.

What that means is both an A both A and B should occur at the same time, which is normally zero delay. And, obviously again, M and must be greater than zero. The thing to notice in all The operators is when does the property buys or renders the property become true. So to say. Now in this example, we are saying that property a be a positive clock, z being true implies starting the same clock, SMB should hold now SMB, so here's your z and it comes at the same time, which is correct. Now, we can come either one clock later to crossfitter or three clocks later, as I just described, that means if we comes one clock later, then the property passes and completes, it does not then look for be on the second or the third go.

If the becomes on the second clock, not the first clock, then the property will pass on the second clock. And and same for the third clock. So the property will match the very first time B is true. It does not give Looking for further bees, which is something important to understand because in other operators, the property will match at the last of the occurrence of a given signal here is the first occurrence of the signal. And here's a very simple application which you can apply. This one says that at pauses of clock, if read request is served it is high is not as sensitive as level sensitive.

They're starting the same clock within one to five globs, either data ready should be asserted should be high, or data boards should be, which makes sense after read requests, either you are going to read or you're going to abort. And so as you can see, range operator is very, very desirable. Because in hardware, more than often you don't know exactly when the next event is going to occur. Now this slide is probably one of the most important slides in this course. We saw multi threaded with single delay earlier in one of the previous lectures. Now let's look at what happens How does the multiple threads work with a range delay operator.

So let's look at this example. But advantage of clock if ready is high, it implies starting same clock within one to five clocks radiate should arrive. Okay. here's here's your timing diagram. You have a clock ready and ready. Now let's say that on this false edge of clock as far as the name of the thread for example, at this was Jeff Clark ready is high as required.

Hear that is high. Then 123 and four crops later ready acreages, and you will see the reason why I call it as one dash two in just a second. But for crops later, radio arrives, as you can see here. And since it was supposed to arrive within one to five clocks, the requirement is met and the property passes. Now let's say that ready comes again, the very next clock. What's going to happen?

This ready is also going to wait from within one to five o'clock to save ready, EQ arrives. But guess what? After this radio arrives, you have one, two, and three clocks and three clocks later it detects that ready check is arrived. So it's going to say it my requirement is met as well. And it's also going to pass. Now see what has happened here to read his game.

But the simulation will show you that they both pass at this particular age. How do you know if the radio four s two arrived, or the radio for the S one arrived? You don't know that both of these are going to pass at the same time and you don't know. What did that radiate for Esther did not write but it sees the radiate that arrived for us one and assume that that is my radio and passes. This is multi threading. And this is very important to understand because what you're getting here, could be not necessarily but could be a false positive evaluation of both threads will end at the same time because both are expecting radiate to occur in a range of delays radiate occurred within that range for both threads.

Pay very close attention to it. So, first question is this is dangerous? How can I be sure that the radio also arrived there is a solution for it. And that solution requires the use of something called local variables. And I have not covered local variables until now. So I will refrain from showing the solution to this problem until we go to local variables, where I'll repeat this example and show you how this can be solved, because this must be solved.

Otherwise, you may get false positives. So here's an application of range delay operator. Let's again as I said dollar meaning infinite can be very useful, because most of the time in complex sequences we will not or you will not know, really, when a certain signal or sequence will follow another signals another sequence, but you do need to make sure that it does occur. So, let's take an example if data is detected, but the pipeline latencies are such that you don't really know exactly when they get or beat will be asserted. But whenever it is asserted, we don't know when that the machine check is asserted the same clock. This is a spec that you will normally see in your mind microarchitecture hardware design specs and you To write an assertion for it.

So here's your tagger here. Okay, let me go. So here's the assertion. What we're saying is if dagger is detected always, when you want to write an assertion, think of what your antecedent is. and carefully design the antecedent. Without a carefully designed antecedent, the rest of the design of the assertion may be very cumbersome or difficult, or even impossible.

So when I did this spec, I'm saying that everything starts with integrity stick. So I say dollar rose tagger. I wanted an edge sensitive, because I only want to detect one tag error only when it occurs. Now I'm saying that I do not know when terabit will be asserted, but it needs to be asserted. So what I'm going to do is bound on one to infinity, I do not know when, but during a starting the next clock up to whenever this T error rate must go high. And whenever it goes high MTech is asserted the same clock.

That's why I have lb lb zero. So, this and this can occur at the same time. Now, you can also use and and Boolean here, which will work the same way. I prefer lb lb zero because what I like to see a continuum, a continuous temporal domain associativity to see the how the temporal domain is moving forward. I personally don't like to make Boolean with temporal domain combinatorially a temporal domain that's just my preference. It's up to you how you want to design it.

There is no difference. There's nothing wrong either way. So here's the dollar dollar rose tagger and note that my arrow stops at the clock edge because it said that was the edge of clock edge that we are going to sample in the pre porn region. If tag error is one and in the previous claw in the people region dagger was zero and hence we detect dollar rose dagger. Then after that one clock later, which is what is 1.1 means, so, after this for one clock, after one dog, we wait forever, they'll be at our bait goes high. It's an insensitive and whenever it goes high, we make sure that MTech also goes high.

And if this relationship is met, then we'll say that the property passes. If not, then the property will fail. If any of this thing fails. Now, just just for the sake of completeness, what happens for example, if the error rate never arrives, we are waiting forever simulation ends the error would never arrived. And if the T error would never arrives, we don't check for the check. Some simulators will give an incomplete assertion some simulators may give a failure and in the 2009 and 2012 LRM that is a concept of strong and weak properties, which I will cover later.

Depending on how you have defined an assertion strong or weak. You will either get a failure at the end of the simulation If the error will never arrives, or you will get an incomplete indication which is dependent on the simulator. But we'll keep that aside but I just want you to make a note of it. That there's a good chance to enter but never arrives and what is it that your simulator is going to do? And that also depends on whether the property is strong or weak. So that's pretty much it for this particular lecture.

Very simple plug a operator we have discussed and you have seen in previous lectures and also the range clock delay operator. Thank you for attending the lecture, and I'll see you soon in the next lectures.

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