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SystemVerilog Assertions and Functional Coverage From Scratch

Learn SystemVerilog assertions and Functional coverage languages, methodologies and applications from scratch.

SystemVerilog Assertions and Functional Coverage From Scratch

Learn SystemVerilog assertions and Functional coverage languages, methodologies and applications from scratch.
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This lecture will provide an introduction to SystemVerilog Assertions, its evolution from PSL, Sugar, etc. and clearly outline course objectives.
We will discuss the basic definition of an Assertion. Its pros and cons and project-wide methodology.
Types of assertions, Immediate and Deferred immediate assertions
This lecture will discuss in-depth, the definitions of sequence, property, assert, and cover. It will also Discuss Overlapping and Non-overlapping Implication Operators. This lecture is foundational to the course.
This lecture describes the phenomenon of the vacuous pass with properties. What is it? And how do you solve this mystery?
This lecture will discuss how SystemVerilog Assertions are sampled in the preponed region of a clock edge. It will discuss the nuances of singly clocked properties.
This lecture discusses the most fundamental semantics of the language - that being the concept of multi-threading and pipelined behavior. It then goes into the discussion of formal and actual arguments and their connectivity. other features discussed are assertion execution terminate system features such as 'disable iff'.
SVA allows you to write properties/assertions for either VHDL or Verilog design. You write the assertions in a file separate from RTL and 'bind' that to either VHDL or Verilog RTL.
Confidently apply knowledge of $rose, $fell, $stable, $past, $changed, $sampled and global clocking past and future sampled value functions.
This lecture discusses the so-called Sampled Value Functions, namely $rose and $fell.
This lecture discusses Sampled Value Functions such as $past, $stable, $changed, $sampled, etc. It also discusses Global clocking PAST and FUTURE sampled value functions.
This lecture discusses the fundamentals of Clock Delay and Clock Delay Range operators.
This lecture dives deep into the Consecutive Repetition Operator.
This lecture dives deep into Non-Consecutive repetition and Non-Consecutive GOTO operators. Shows the similarity and differences between the two operators.
This lecture discusses the operators "throughout' and 'within'.
This lecture discusses the operators 'and', 'or' and 'intersect' as applied to procedural code as well as a concurrent assertion.
Continuing with the previous lecture, in this lecture we discuss further nuances of 'and', 'or' and 'intersect' operators.
This lecture discusses the important concept of 'first_match' and its effective use in an Antecedent. It then follows with if-then-else, iff, and 'implies' features.
$onehot, $onehot0, $isunknown, $countones Assertion execution control tasks: $assertoff, $asserton, $assertkill, $assertpassoff, $assertpasson, $assertfailoff, $assertfailon, $assertnonvacuouson, $assertvacuousoff, $assertcontrol
Multiply clocked sequences. Multiply clocked properties: ‘and’, ‘or’, ‘not’ operators. Multiple Clock resolution
This lecture continues with the previous lecture on multiple clocks
This lectures dives deep into SystemVerilog Assertions (SVA) 'Local Variables'. Plenty of applications are given.
Here we will address very fine detail on the pitfalls of incorrectly using local data assignment in 'and' and 'or' of sequences.
This lecture discusses 'expect', 'assume', Blocking 'action block' etc. important features of SVA
This lecture shows how to write SVA assertion for an Asynchronous FIFO.
A few misc. topics, including effective use of 'attaching' (or calling) subroutines on the match of a sequence, use of sequence in Verilog procedural block sensitivity list or as an event trigger. Also, I am discussing how cyclic dependency work in SVA
In this lecture we will explore how recursive properties work and how to apply that in real life applications.
This lecture discusses the IEEE-1800 LRM 2009 and 2012 features such as 'let declarations' and 'checker'
In this lecture, we'll discuss some of the legal and illegal ways to assign variables; indexing loops, etc.
We will explore the concept of strong and weak properties. Also, we'll explore operators such as 'followed-by', 'always' and 'eventually'
1:14:33
A synchronous FIFO design is presented and questions are posed for which you have to write assertions.
An up-down counter design is presented and questions are posed for which you have to write assertions.
In this quiz, a simple bus protocol is provided. You will learn to write assertions to see that the bus protocol adheres to its specification
This Quiz describes a simple PCI system. We will see how to verify the PCI Read Protocol with various assertions.
This lecture will establish the role of Functional Coverage under the IEEE-1800 SystemVerilog umbrella. It will also highlight the difference between code coverage and functional coverage.
This lecture will show you the Functional Coverage Methodology which encompasses, SystemVerilog Assertions (SVA) 'cover' + SystemVerilog Functional Coverage + Code Coverage. It also shows you how you can automate Test => Simulation => Coverage Evaluation => Test enhancement loop to reach a 100% coverage goal.
in-depth discussion on syntax/semantics and applications of SystemVerilog 'covergroup' and 'coverpoint'
in-depth discussion on syntax/semantics and applications of SystemVerilog 'coverpoint' 'bins'
in-depth discussion on syntax/semantics and applications of SystemVerilog 'cross' coverage
in-depth discussion on syntax/semantics and applications of SystemVerilog 'transition' coverage.
This lecture further explores nuances of 'bins' specifically addressing how to manage and filter 'bins'
This lectures describes various features and nuances of embedding a covergroup in a class and how to create array of covergroup instances and hierarchical references from embedded covergroups.
In this lecture, you will learn about 'what you should cover', 'when you should cover', and the performance implications thereof.
This lecture describes various methods (functions) available in the language to query for coverage. Coverage of covergroups, coverpoints and/or their instances. It also describes the user defined sample() method.
In this lecture, you will learn about Coverage options such as 'weight' 'auto_bin_max' etc. instance specific options. Examples will solidify the usage of these options

SystemVerilog Assertions and Functional Coverage is a comprehensive from-scratch course on Assertions and Functional coverage languages that cover features of SV LRM 2005/2009 and 2012. The course does not require any prior knowledge of OOP or UVM. The course is taught by a 30 year veteran in the design of CPU and SoC who has published the second edition of a book on SVA and FC in 2016 and holds 18 U.S. patents in design verification. The course has 50+ lectures and is 12+ hours in length that will take you to step by step through the learning of the languages.

The knowledge gained from this course will help you find and cover those critical and hard to find design bugs. SystemVerilog Assertions and Functional coverage are very important parts of overall functional verification methodology, and all verification engineers need this knowledge to be successful. The knowledge of SVA and FC will be highlights of your resume when seeking a challenging job or project. The course offers a step-by-step guide to learning of SVA and FC with plenty of real-life applications to help you apply SVA and FC to your project in the shortest possible time. SVA and FC help critical aspect of Functional and Sequential domain coverage which is not possible with code coverage.

Requirements

  • You should have basic knowledge of Verilog
  • You should have basic knowledge of hardware design and verification
  • No knowledge of SystemVerilog OOP (object-oriented programming) required
  • No knowledge of SystemVerilog UVM (Universal Verification methodology) required.
This lecture will provide an introduction to SystemVerilog Assertions, its evolution from PSL, Sugar, etc. and clearly outline course objectives.
We will discuss the basic definition of an Assertion. Its pros and cons and project-wide methodology.
Types of assertions, Immediate and Deferred immediate assertions
This lecture will discuss in-depth, the definitions of sequence, property, assert, and cover. It will also Discuss Overlapping and Non-overlapping Implication Operators. This lecture is foundational to the course.
This lecture describes the phenomenon of the vacuous pass with properties. What is it? And how do you solve this mystery?
This lecture will discuss how SystemVerilog Assertions are sampled in the preponed region of a clock edge. It will discuss the nuances of singly clocked properties.
This lecture discusses the most fundamental semantics of the language - that being the concept of multi-threading and pipelined behavior. It then goes into the discussion of formal and actual arguments and their connectivity. other features discussed are assertion execution terminate system features such as 'disable iff'.
SVA allows you to write properties/assertions for either VHDL or Verilog design. You write the assertions in a file separate from RTL and 'bind' that to either VHDL or Verilog RTL.
Confidently apply knowledge of $rose, $fell, $stable, $past, $changed, $sampled and global clocking past and future sampled value functions.
This lecture discusses the so-called Sampled Value Functions, namely $rose and $fell.
This lecture discusses Sampled Value Functions such as $past, $stable, $changed, $sampled, etc. It also discusses Global clocking PAST and FUTURE sampled value functions.
This lecture discusses the fundamentals of Clock Delay and Clock Delay Range operators.
This lecture dives deep into the Consecutive Repetition Operator.
This lecture dives deep into Non-Consecutive repetition and Non-Consecutive GOTO operators. Shows the similarity and differences between the two operators.
This lecture discusses the operators "throughout' and 'within'.
This lecture discusses the operators 'and', 'or' and 'intersect' as applied to procedural code as well as a concurrent assertion.
Continuing with the previous lecture, in this lecture we discuss further nuances of 'and', 'or' and 'intersect' operators.
This lecture discusses the important concept of 'first_match' and its effective use in an Antecedent. It then follows with if-then-else, iff, and 'implies' features.
$onehot, $onehot0, $isunknown, $countones Assertion execution control tasks: $assertoff, $asserton, $assertkill, $assertpassoff, $assertpasson, $assertfailoff, $assertfailon, $assertnonvacuouson, $assertvacuousoff, $assertcontrol
Multiply clocked sequences. Multiply clocked properties: ‘and’, ‘or’, ‘not’ operators. Multiple Clock resolution
This lecture continues with the previous lecture on multiple clocks
This lectures dives deep into SystemVerilog Assertions (SVA) 'Local Variables'. Plenty of applications are given.
Here we will address very fine detail on the pitfalls of incorrectly using local data assignment in 'and' and 'or' of sequences.
This lecture discusses 'expect', 'assume', Blocking 'action block' etc. important features of SVA
This lecture shows how to write SVA assertion for an Asynchronous FIFO.
A few misc. topics, including effective use of 'attaching' (or calling) subroutines on the match of a sequence, use of sequence in Verilog procedural block sensitivity list or as an event trigger. Also, I am discussing how cyclic dependency work in SVA
In this lecture we will explore how recursive properties work and how to apply that in real life applications.
This lecture discusses the IEEE-1800 LRM 2009 and 2012 features such as 'let declarations' and 'checker'
In this lecture, we'll discuss some of the legal and illegal ways to assign variables; indexing loops, etc.
We will explore the concept of strong and weak properties. Also, we'll explore operators such as 'followed-by', 'always' and 'eventually'
1:14:33
A synchronous FIFO design is presented and questions are posed for which you have to write assertions.
An up-down counter design is presented and questions are posed for which you have to write assertions.
In this quiz, a simple bus protocol is provided. You will learn to write assertions to see that the bus protocol adheres to its specification
This Quiz describes a simple PCI system. We will see how to verify the PCI Read Protocol with various assertions.
This lecture will establish the role of Functional Coverage under the IEEE-1800 SystemVerilog umbrella. It will also highlight the difference between code coverage and functional coverage.
This lecture will show you the Functional Coverage Methodology which encompasses, SystemVerilog Assertions (SVA) 'cover' + SystemVerilog Functional Coverage + Code Coverage. It also shows you how you can automate Test => Simulation => Coverage Evaluation => Test enhancement loop to reach a 100% coverage goal.
in-depth discussion on syntax/semantics and applications of SystemVerilog 'covergroup' and 'coverpoint'
in-depth discussion on syntax/semantics and applications of SystemVerilog 'coverpoint' 'bins'
in-depth discussion on syntax/semantics and applications of SystemVerilog 'cross' coverage
in-depth discussion on syntax/semantics and applications of SystemVerilog 'transition' coverage.
This lecture further explores nuances of 'bins' specifically addressing how to manage and filter 'bins'
This lectures describes various features and nuances of embedding a covergroup in a class and how to create array of covergroup instances and hierarchical references from embedded covergroups.
In this lecture, you will learn about 'what you should cover', 'when you should cover', and the performance implications thereof.
This lecture describes various methods (functions) available in the language to query for coverage. Coverage of covergroups, coverpoints and/or their instances. It also describes the user defined sample() method.
In this lecture, you will learn about Coverage options such as 'weight' 'auto_bin_max' etc. instance specific options. Examples will solidify the usage of these options

About the instructors

 

Ashok Mehta

Technology Adviser, 18 US Patents
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Ashok Mehta has worked in the CPU/SoC design and verification field for over 30 years at DEC, DG, INTEL, APPLIED MICRO (AMCC) and TSMC.

Ashok is author of the popular book “SystemVerilog Assertions and Functional Coverage: A guide to language, methodology and applications - Third Edition”. Springer 2020

Also, author of popular book "ASIC/SoC Functional Design Verification: A comprehensive guide to technologies and methodologies". Springer 2017

Ashok holds 18 Granted U.S. Patents in the field of SoC and 3D-IC design verification.

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