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SystemVerilog Assertions and Functional Coverage From Scratch

Learn SystemVerilog assertions and Functional coverage languages, methodologies and applications from scratch.

SystemVerilog Assertions and Functional Coverage From Scratch

Learn SystemVerilog assertions and Functional coverage languages, methodologies and applications from scratch.
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About the Class

SystemVerilog Assertions and Functional Coverage is a comprehensive from-scratch course on Assertions and Functional coverage languages that cover features of SV LRM 2005/2009 and 2012. The course does not require any prior knowledge of OOP or UVM. The course is taught by a 30 year veteran in the design of CPU and SoC who has published the second edition of a book on SVA and FC in 2016 and holds 18 U.S. patents in design verification. The course has 50+ lectures and is 12+ hours in length that will take you to step by step through the learning of the languages.

The knowledge gained from this course will help you find and cover those critical and hard to find design bugs. SystemVerilog Assertions and Functional coverage are very important parts of overall functional verification methodology, and all verification engineers need this knowledge to be successful. The knowledge of SVA and FC will be highlights of your resume when seeking a challenging job or project. The course offers a step-by-step guide to learning of SVA and FC with plenty of real-life applications to help you apply SVA and FC to your project in the shortest possible time. SVA and FC help critical aspect of Functional and Sequential domain coverage which is not possible with code coverage.

Author

 

Ashok Mehta

Technology Adviser, 18 US Patents
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Ashok Mehta has worked in the CPU/SoC design and verification field for over 30 years at DEC, DG, INTEL, APPLIED MICRO (AMCC) and TSMC. Ashok is author of the popular book “SystemVerilog Assertions and Functional Coverage: A guide to language, methodology and applications - Third Edition”. Springer 2020 Also, author of popular book "ASIC/SoC...

Class Requirements

  • You should have basic knowledge of Verilog
  • You should have basic knowledge of hardware design and verification
  • No knowledge of SystemVerilog OOP (object-oriented programming) required
  • No knowledge of SystemVerilog UVM (Universal Verification methodology) required.

Class Contents

What's Included

Level: All levels
Duration: 11 hours 58 minutes
50 Videos
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